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Design a clock divider circuit to produce a 250kHz signal from the Xilinx 16MHz clock and write it in Verilog. Modifications by N. Weaver and E. Caspi. Verilog related modifications by Yury Markovskiy and Jack Sampson Spring 2002. For the prelab do the following 1. Read the data sheets for the following Xilinx library components available in the Xilinx Library Guide linked from the course web page CC16CE CB4CLE SR8RE BUFG. Understand their operation and special inputs and outputs e.g. CE TC...
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