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This control logic has been created for you as the dactls block in the schematic dac.sch Figure 3. dg dactls DAC Vg FPGA Figure 3 Block diagram of DAC connection within the FPGA. In your case Vdd 3. 3V. In dac.sch the input to dactls is tied to the 8 switches on the Basys2 board. It is to di erentiate it from the 12 V VCC signal that you will use in the next lab. From now on Signal Name VDD VCC Voltage 12 V Source Driven by FPGA Driven by Power Supply Pin a DAC Module Name A1 B1 A2 B2 GND...
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