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Port K Port J XMEGA RE WE ALE1 Port H ALE2 CS3 CS2 CS1 CS0 CLK EBI Reset 16k x 8 bit RAM A -A0 D7-D0 OE CS 8k x 8 Port ROM A-A0 8-bit Latch Q7-Q0 G Flip-Flop Tri-State In7-0 Out7-0 22 2. Note the two CLK signals on this device F1 and F2. Note R/ W also that the high part of the address bus is tri-stated during the second half of the A7-A0 / F1-cycle. Port Addr Range 0x 1D 7000 - 0x 0b - 0b 8K 8k x 8 ROM Addr Range 16K 16k x 8 SRAM Addr Range 0x - 0x 1. When PC3 goes false low start the...
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